FIG. 1 shows a typical prior art, high power, lateral, integrated PNP transistor. In the exemplary device of FIG. 1, a P substrate 10 has an N epitaxial layer 20 formed thereon. A highly doped P+ emitter 30 is formed in the surface of epitaxial layer 20.
Surrounding P+ emitter 30, but separated therefrom by a portion of N epitaxial layer 20, is a P+ collector 40.
To turn the PNP bipolar transistor on, the P+ emitter 30 is forward biased with respect to the N epitaxial layer 20, acting as a base, while P+ collector 40 is reverse biased with respect to the base.
To provide an ohmic connection to the base region of the transistor, a highly doped N+ contact region 50 may be formed on the surface of epitaxial layer 20.
When the transistor is biased on, there will be a minority carrier hole current in N epitaxial layer 20 due to the forward biasing of the P+ emitter 30 with respect to N epitaxial layer 20. Most of these minority carrier holes injected into epitaxial layer 20 will be collected by the P+ collector 40, having a negative voltage applied thereto with respect to the epitaxial layer 20 base. A small portion of these holes will be withdrawn via N+ contact 50 as base current.
Ideally, all holes injected by the emitter 30 into N epitaxial layer 20 will be withdrawn by either the collector 40 or the base contact 50. However, as the flow of holes shown in dashed lines in FIG. 1 illustrates, without any buried region, the electrical fields created by the biasing of the device and the proximity of the substrate to emitter 30 results in a small flow of holes reaching the epitaxial layer/substrate interface and being injected into substrate 10. This hole current will then flow through substrate 10 to a terminal connected to the substrate. Such a hole current in P substrate 10 generates a voltage differential within the substrate which may affect other devices formed in the substrate in the form of cross-talk (modulation), noise, or latchup. Further, substrate current wastes power and generates heat.
In an attempt to block these minority carriers from entering the substrate, the prior art forms a highly doped buried region, such as N+ buried region 60 in FIG. 1. Most holes injected into N+ buried region 60 are recombined in N+ buried region 60 and consequently do not penetrate into substrate 10. Although, N+ buried region 60 desirably reduces substrate current, the holes injected into N+ buried region 60 undesirably constitute a loss of current and hence a lowering of the beta of the primary lateral PNP transistor.
N+ buried region 60 also acts to reduce the beta of any parasitic transistor formed where the P substrate 10 acts as an emitter or collector of the parasitic transistor. However, there still exists a parasitic PNP transistor to the substrate.
P+ isolation diffusions 70 isolate the area of the epitaxial layer containing the lateral integrated PNP transistors.
If N+ buried region 60 is connected to a base terminal via N+ sinkers 80, this would allow buried region 60 to act as an additional base contact region. By connecting buried region 60 to the base terminal, N+ base contact region 50 may be deleted if the substrate can serve as a common node or ground.
As is well known, as the thickness of N epitaxial layer 20 decreases, or the distance between the emitter 30 and collector 40 are spaced further apart to achieve desired operating characteristics, more and more minority carriers will be injected into any buried layer, thus undesirably reducing the beta and efficiency of the lateral PNP transistor. Further, a percentage of these minority carriers will be undesirably injected into the substrate, creating a substrate current.
In addition to the leakage to the substrate as indicated, integrated power PNP transistors incorporating an N buried layer inherently include a parasitic PNP to the substrate, with the surface P+ region serving as the emitter, the N epitaxial and buried layer acting as a base, and the P substrate acting as a collector. Where the prime power transistor is handling 3.5 amps, if the parasitic transistor only has a beta of 0.1, it will result in 350 ma being dumped into the substrate.
With low voltage or low power PNP bipolar transistors, such as those operating at under 10 volts or under 1 ma of current, the proximity of the emitter and collector regions, the shallow depth of these regions relative to the epitaxial layer thickness, the low currents involved, and the low electric fields generated cause very few minority carriers to be injected into the substrate. Thus, the added expense of forming a buried layer, such as buried layer 60 in FIG. 1, is not justified in many cases.
FIG. 2 illustrates a conventional low voltage, integrated NPN bipolar transistor using a buried N collector region 84, but such a structure is clearly unsuitable for forming PNP devices in an N epitaxial layer and unsuitable for high voltage applications due to the relatively narrow width of the diffused P base region 86.
Forming a number of high power, integrated bipolar transistors in parallel on a single chip would increase any undesirable substrate current, and the undesirable effects of substrate current will be exacerbated.
Further, in such applications where high power, integrated devices are formed on the same integrated circuit as low voltage devices, such as where the high power devices act as a high power output circuit under control of logic circuitry on the same chip, the problems with substrate current from high power devices and the parasitic PNP action to the substrate are extremely significant due to the sensitivity of the low voltage logic devices to variations in substrate current.
What is needed is an efficient, high power, integrated PNP bipolar transistor structure which virtually eliminates any undesirable current in the substrate and any parasitic PNP action so that these high power devices may be incorporated on integrated circuits with very sensitive low power logic devices.